As system data rates and clock frequencies continue to increase, signal integrity issues are becoming more of a concern. For example, certain signal integrity issues may be related to the output impedance of the drivers that drive signals from the integrated circuit (i.e., driving signals off-chip).
Consequently, as a specific example, the next generation of high-speed synchronous memory devices (e.g., DDR2 or GDDR3) have output drivers with adjustable output impedances. The output impedance of the output drivers may be adjusted after the device is powered up by loading bit patterns into registers inside the memory device. The apparent intent of this scheme is that a memory controller (e.g., implemented within a programmable logic device, application specific integrated circuit, or other type of circuit, such as a processor) will measure the output impedance of the output drivers on the memory device. The memory controller will then load the registers in the memory device with the appropriate bit patterns to optimize the output impedance of the output drivers. Thus, optimum signal integrity may be achieved and memory read access times may be minimized.
The adjustable output driver output impedance feature may be applied not only to memory devices, but also to other types of integrated circuits that may be required to provide information. However, the problem exists generally as to the appropriate technique for a first device to measure the output impedance of the output drivers on another device that is connected to the first device. For example, for the memory device example above, it may be required that the memory controller must also function to measure the output impedance of the output drivers of the memory device. As a result, there is a need for output impedance measurement techniques.